With the continually increasing demand for smaller circuit structures and faster device performance, semiconductor wafer manufacturing has grown more complicated. With the increased complexity, each ‘recipe’ requires more and more processes, or ‘transitions,’ to manufacture a wafer. With each transition, the possibility of a fault from the processing is introduced.
Typically, some data is collected before, during, and/or after some or all transitions. However, this approach is costly, time consuming, and frequently requires 40 or more engineers present to monitor the transitions, as well as the testing and analysis. Additionally, the data is not always accurate due to trimming and windowing of trace data in small time frames, using sequential statistics math to make fault detection classification (FDC) models.
It is desirable to develop simple graphical recipe transition representation methods of real-time fault detection and post-process analysis methods for semiconductor wafer manufacturing to monitor for known unwanted or new baseline performance changes.